Xilinx PlanAhead/XPS annoyances

So I know Xilinx wants everybody to move on to Vivado now, but being wary of new software, I am still using PlanAhead. One very annoying thing about the whole IP core business is figuring out how to roll your own without failing the implementation stage. I just did one where I could swear that the presence of an underscore in the filename killed it. Yep.


When I make AXI peripherals, I’ve been putting my logic into a hierarchy that I then instantiate inside a Xilinx-generated AXI template. Otherwise it’s hard to test without using a BFM. In order to do it this way, I have to add one line to the MPD with the name of the module. It’s the bottom one here:

lib proc_common_v3_00_a  all 
lib axi_lite_ipif_v1_01_a  all 
lib fifotest_v1_00_a user_logic vhdl
lib fifotest_v1_00_a fifotest vhdl
lib fifotest_v1_00_a fifotestcore vhdl

And would you believe that when the module was named “fifotest_core”, it didn’t want to work?

That one was a pure HDL module (it has a Xilinx FIFO instance, but that’s easy). What’s really annoying is when you want to put a Core Generator module into your peripheral. Apparently you need to put your NGCs into a /netlist folder, but I haven’t figured out how to get the PAO and MPD and such correct by hand. So far I’ve ended up completely re-importing everything in the XPS wizard, which is a little messy and annoying, but works. Par for the course I suppose.

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